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KAD5512P
Data Sheet March 4, 2009 FN6807.2
Low Power 12-Bit, 250/210/170/125MSPS ADC
The KAD5512P is the low-power member of the KAD5512 family of 12-bit analog-to-digital converters. Designed with Intersil's proprietary FemtoChargeTM technology on a standard CMOS process, the family supports sampling rates of up to 250MSPS. The KAD5512P is part of a pin-compatible portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging from 125MSPS to 500MSPS. A serial peripheral interface (SPI) port allows for extensive configurability, as well as fine control of various parameters such as gain and offset. Digital output data is presented in selectable LVDS or CMOS formats. The KAD5512P is available in 72- and 48-contact QFN packages with an exposed paddle. Operating from a 1.8V supply, performance is specified over the full industrial temperature range (-40C to +85C).
Features
* Pin-Compatible with the KAD5512HP Family, Operating at Half the Power * Programmable Gain, Offset and Skew Control * 1.3GHz Analog Input Bandwidth * 60fs Clock Jitter * Over-Range Indicator * Selectable Clock Divider: /1, /2 or /4 * Clock Phase Selection * Nap and Sleep Modes * Two's Complement, Gray Code or Binary Data Format * SDR/DDR LVDS-Compatible or LVCMOS Outputs * Programmable Built-in Test Patterns * Single-Supply 1.8V Operation * Pb-Free (RoHS Compliant)
Key Specifications
* SNR = 66.1dBFS for fIN = 105MHz (-1dBFS) * SFDR = 87dBc for fIN = 105MHz (-1dBFS) * Total Power Consumption - 267/219mW @ 250/125MSPS (SDR Mode) - 234/189mW @ 250/125MSPS (DDR Mode)
CLKDIV OVDD AVDD
Applications
* Power Amplifier Linearization * Radar and Satellite Antenna Array Processing * Broadband Communications * High-Performance Data Acquisition * Communications Test Equipment * WiMAX and Microwave Receivers
CLKP CLKN
CLOCK GENERATION
CLKOUTP CLKOUTN
Pin-Compatible Family
MODEL KAD5514P-25 KAD5514P-21 KAD5514P-17 KAD5514P-12 KAD5512P-50 RESOLUTION 14 14 14 14 12 12 12 12 12 10 SPEED (MSPS) 250 210 170 125 500 250 210 170 125 500
D[11:0]P VINP SHA VINN VCM 1.25V + - 12-BIT 250 MSPS ADC DIGITAL ERROR CORRECTION LVDS/CMOS DRIVERS D[11:0]N ORP ORN OUTFMT OUTMODE
SPI CONTROL
NAPSLP
OVSS
AVSS
CSB SCLK SDIO SDO
KAD5512P-25, KAD5512HP-25 KAD5512P-21, KAD5512HP-21 KAD5512P-17, KAD5512HP-17 KAD5512P-12, KAD5512HP-12 KAD5510P-50
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
KAD5512P Ordering Information
PART NUMBER KAD5512P-25Q72 (Note 2) KAD5512P-21Q72 (Note 2) KAD5512P-17Q72 (Note 2) KAD5512P-12Q72 (Note 2) KAD5512P-25Q48 (Note 1) KAD5512P-21Q48 (Note 1) KAD5512P-17Q48 (Note 1) KAD5512P-12Q48 (Note 1) NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PART MARKING KAD5512P-25 Q72EP-I KAD5512P-21 Q72EP-I KAD5512P-17 Q72EP-I KAD5512P-12 Q72EP-I KAD5512P-25 Q48EP-I KAD5512P-21 Q48EP-I KAD5512P-17 Q48EP-I KAD5512P-12 Q48EP-I SPEED (MSPS) 250 210 170 125 250 210 170 125 TEMP. RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-Free) 72 Ld QFN 72 Ld QFN 72 Ld QFN 72 Ld QFN 48 Ld QFN 48 Ld QFN 48 Ld QFN 48 Ld QFN PKG. DWG. # L72.10X10D L72.10X10D L72.10X10D L72.10X10D L48.7X7E L48.7X7E L48.7X7E L48.7X7E
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FN6807.2 March 4, 2009
KAD5512P Table of Contents
Absolute Maximum Ratings ......................................... 4 Thermal Information...................................................... 4 Electrical Specifications ............................................... 4 Digital Specifications .................................................... 6 Timing Diagrams ........................................................... 7 Switching Specifications .............................................. 7 Pinout/Package Information......................................... 9 Pin Descriptions - 72QFN........................................... Pinout ......................................................................... Pin Descriptions - 48QFN........................................... Pinout ......................................................................... 9 10 11 12 Serial Peripheral Interface ........................................... 22 SPI Physical Interface................................................ SPI Configuration....................................................... Device Information ..................................................... Indexed Device Configuration/Control ....................... Global Device Configuration/Control.......................... Device Test ................................................................ SPI Memory Map ....................................................... 22 22 23 23 24 25 26
Equivalent Circuits ....................................................... 27 Layout Considerations................................................. 28 Split Ground and Power Planes................................. Clock Input Considerations ........................................ Exposed Paddle......................................................... Bypass and Filtering .................................................. LVDS Outputs ............................................................ LVCMOS Outputs ...................................................... Unused Inputs............................................................ 28 28 28 28 28 28 28
Typical Performance Curves ........................................ 13 Theory of Operation ...................................................... 16 Functional Description ................................................. 16 Power-On Calibration .................................................. 16 User-Initiated Reset ..................................................... 17 Analog Input ................................................................ 17 Clock Input .................................................................. 18 Jitter ............................................................................. 19 Voltage Reference....................................................... 19 Digital Outputs ............................................................. 19 Over Range Indicator .................................................. 19 Power Dissipation ........................................................ 19 Nap/Sleep.................................................................... 19 Data Format ................................................................ 20
Definitions ..................................................................... 29 Revision History ........................................................... 30 Package Outline Drawings........................................... 31 L48.7x7E.................................................................... 31 L72.10x10D................................................................ 32
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FN6807.2 March 4, 2009
KAD5512P
Absolute Maximum Ratings
AVDD to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V AVSS to OVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V Analog Inputs to AVSS. . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Clock Inputs to AVSS. . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Logic Inputs to OVSS. . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) 48 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 72 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40C to +85C (typical specifications at +25C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). KAD5512P-25 PARAMETER SYMBOL CONDITIONS MIN TYP KAD5512P-21 TYP KAD5512P-17 TYP KAD5512P-12 TYP MAX UNITS
MAX MIN
MAX MIN
MAX MIN
DC SPECIFICATIONS (Note 4) Analog Input Full-Scale Analog Input Range Input Resistance Input Capacitance Full Scale Range Temp. Drift Input Offset Voltage Gain Error Common-Mode Output Voltage Clock Inputs Inputs Common Mode Voltage CLKP,CLKN Input Swing Power Requirements 1.8V Analog Supply Voltage 1.8V Digital Supply Voltage 1.8V Analog Supply Current 1.8V Digital Supply Current (SDR) (Note 4) 1.8V Digital Supply Current (DDR) (Note 4) AVDD OVDD IAVDD
I OVDD
VFS RIN CIN AVTC VOS EG VCM
Differential Differential Differential Full Temp
1.40
1.47 1000 1.8 90
1.54 1.40
1.47 1000 1.8 90
1.54 1.40
1.47 1000 1.8 90
1.54 1.40
1.47 1000 1.8 90
1.54
VP-P pF ppm/C
-10
2 0.6
10
-10
2 0.6
10
-10
2 0.6
10
-10
2 0.6
10
mV %
435
535
635
435
535
635
435
535
635
435
535
635
mV
0.9 1.8
0.9 1.8
0.9 1.8
0.9 1.8
V V
1.7 1.7
1.8 1.8 90
1.9 1.9 96 62
1.7 1.7
1.8 1.8 83 56
1.9 1.9 89 60
1.7 1.7
1.8 1.8 77 54
1.9 1.9 82 58
1.7 1.7
1.8 1.8 69 52
1.9 1.9 74 56
V V mA mA
3mA LVDS
58
I
OVDD
3mA LVDS
39
38
36
35
mA
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FN6807.2 March 4, 2009
KAD5512P
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40C to +85C (typical specifications at +25C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). (Continued) KAD5512P-25 PARAMETER Power Supply Rejection Ratio SYMBOL PSRR CONDITIONS 30MHz, 200mVP-P signal on AVDD MIN TYP -36 KAD5512P-21 TYP -36 KAD5512P-17 TYP -36 KAD5512P-12 TYP -36 MAX UNITS dB
MAX MIN
MAX MIN
MAX MIN
Total Power Dissipation Normal Mode (SDR) Normal Mode (DDR) Nap Mode Sleep Mode PD PD PD PD 3mA LVDS 3mA LVDS 267 234 84 15 95 20 286 252 219 80 14 91 19 271 237 204 78 13 88 19 253 219 189 74 13 84 19 235 mW mW mW mW
AC SPECIFICATIONS (Note 5) Differential Nonlinearity Integral Nonlinearity Minimum Conversion Rate (Note 6) Maximum Conversion Rate Signal-to-Noise Ratio DNL INL fS MIN -0.8 -2.0 0.3 0.8 0.8 2.0 40 -0.8 -2.0 0.3 1.1 0.8 2.0 40 -0.8 -2.0 0.3 1.1 0.8 2.0 40 -0.8 -2.5 0.3 1.4 0.8 2.5 40 LSB LSB MSPS
fS MAX SNR fIN = 10MHz fIN = 105MHz fIN = 190MHz fIN = 364MHz fIN = 695MHz fIN = 995MHz
250 66.1 64.0 66.1 65.9 65.4 63.8 62.6 65.3 63.3 65.3 64.6 63.9 56.9 49.6 10.6 10.3 10.6 10.4 10.3 9.2 7.9
210 66.6 64.5 66.6 66.3 65.7 64.2 62.4 65.6 63.8 65.6 65.2 64.3 57.2 44.9 10.6 10.4 10.6 10.5 10.4 9.2 7.2
170 66.9 65.0 66.9 66.7 66.1 64.4 62.7 66.8 64.3 65.8 65.5 64.7 57.9 48.3 10.6 10.5 10.6 10.6 10.5 9.3 7.7
125 67.1 65.2 67.1 66.8 66.1 64.1 62.4 66.3 64.3 66.3 65.6 64.1 57.4 49.3 10.7 10.5 10.7 10.6 10.4 9.2 7.9
MSPS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits Bits Bits Bits
Signal-to-Noise and Distortion
SINAD
fIN = 10MHz fIN = 105MHz fIN = 190MHz fIN = 364MHz fIN = 695MHz fIN = 995MHz
Effective Number of Bits
ENOB
fIN = 10MHz fIN = 105MHz fIN = 190MHz fIN = 364MHz fIN = 695MHz fIN = 995MHz
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FN6807.2 March 4, 2009
KAD5512P
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40C to +85C (typical specifications at +25C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). (Continued) KAD5512P-25 PARAMETER Spurious-Free Dynamic Range SYMBOL SFDR CONDITIONS fIN = 10MHz fIN = 105MHz fIN = 190MHz fIN = 364MHz fIN = 695MHz fIN = 995MHz Intermodulation Distortion Word Error Rate Full Power Bandwidth NOTES: 4. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output. 5. AC Specifications apply after internal calibration of the ADC is invoked at the given sample rate and temperature. Refer to "Power-On Calibration" on page 16 and "User-Initiated Reset" on page 17 for more details. 6. The DLL Range setting must be changed for low speed operation. See "Serial Peripheral Interface" on page 22 for more detail. IMD fIN = 70MHz fIN = 170MHz WER FPBW 70 MIN TYP 83.0 87 79.4 76.1 60.6 50.7 -85.7 -97.1 10-12 1.3 70 KAD5512P-21 TYP 81.4 86.2 80.5 76.1 61.4 46.4 -92.1 -87.1 10-12 1.3 70 KAD5512P-17 TYP 78.8 84.4 81.8 78.2 61.6 49.2 -94.5 -91.6 10-12 1.3 70 KAD5512P-12 TYP 79.6 86 82.0 71.8 61.6 50.3 -95.1 -85.7 10-12 1.3 GHz MAX UNITS dBc dBc dBc dBc dBc dBc dBFS dBFS
MAX MIN
MAX MIN
MAX MIN
Digital Specifications
PARAMETER INPUTS Input Current High (SDIO,RESETN) Input Current Low (SDIO,RESETN) Input Voltage High (SDIO, RESETN) Input Voltage Low (SDIO, RESETN) Input Current High (OUTMODE, NAPSLP, CLKDIV, OUTFMT) (Note 9) Input Current Low (OUTMODE, NAPSLP, CLKDIV, OUTFMT) Input Capacitance LVDS OUTPUTS Differential Output Voltage Output Offset Voltage Output Rise Time Output Fall Time CMOS OUTPUTS Voltage Output High Voltage Output Low Output Rise Time Output Fall Time VOH VOL tR tF IOH = -500A IOL = 1mA OVDD - 0.3 OVDD - 0.1 0.1 1.8 1.4 0.3 V V ns ns VT VOS tR tF 3mA Mode 3mA Mode 950 620 965 500 500 980 mVP-P mV ps ps IIH IIL VIH VIL IIH IIL CDI 15 -40 25 25 3 VIN = 1.8V VIN = 0V 0 -25 1.17 .63 40 -15 1 -12 10 -5 A A V V A A pF SYMBOL CONDITIONS MIN TYP MAX UNITS
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FN6807.2 March 4, 2009
KAD5512P Timing Diagrams
SAMPLE N INP INP SAMPLE N
INN tA CLKN CLKP tCPD CLKOUTN CLKOUTP tDC D[10/8/6/4/2/0]P D[10/8/6/4/2/0]N
ODD BITS N-L
INN tA CLKN CLKP LATENCY = L CYCLES tCPD CLKOUTN CLKOUTP tDC
EVEN BITS N
LATENCY = L CYCLES
tPD
EVEN BITS ODD BITS EVEN BITS ODD BITS EVEN BITS N-L + 1 N-L + 1 N-L + 2 N-L + 2 N-L
D[11/0]P D[11/0]N
tPD
DATA N-L DATA N-L + 1 DATA N
FIGURE 1A. DDR FIGURE 1. LVDS TIMING DIAGRAMS
FIGURE 1B. SDR
SAMPLE N INP INP
SAMPLE N
INN tA CLKN CLKP tCPD CLKOUT tDC tPD D[10/8/6/4/2/0]
ODD BITS N-L EVEN BITS ODD BITS N-L N-L + 1 EVEN BITS ODD BITS EVEN BITS N-L + 1 N-L + 2 N-L + 2 EVEN BITS N
INN tA CLKN CLKP LATENCY = L CYCLES tCPD CLKOUT tDC tPD D[11/0]
DATA N-L DATA N-L + 1 DATA N
LATENCY = L CYCLES
FIGURE 2A. DDR FIGURE 2. CMOS TIMING DIAGRAM
FIGURE 2B. SDR
Switching Specifications
PARAMETER ADC OUTPUT Aperture Delay RMS Aperture Jitter Output Clock to Data Propagation Delay, LVDS Mode (Note 10) DDR Rising Edge DDR Falling Edge SDR Falling Edge Output Clock to Data Propagation Delay, CMOS Mode (Note 10) DDR Rising Edge DDR Falling Edge SDR Falling Edge tA jA tDC tDC tDC tDC tDC tDC -260 -160 -260 -220 -310 -310 375 60 -50 10 -40 -10 -90 -50 120 230 230 200 110 200 ps fs ps ps ps ps ps ps CONDITION SYMBOL MIN TYP MAX UNITS
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FN6807.2 March 4, 2009
KAD5512P Switching Specifications (Continued)
PARAMETER Latency (Pipeline Delay) Over Voltage Recovery SPI INTERFACE (Notes 7, 8) SCLK Period Write Operation Read Operation SCLK Duty Cycle (tHI/tCLK or tLO/tCLK) SCLK to CSB Setup Time SCLK to CSB Hold Time SCLK to Data Setup Time SCLK to Data Hold Time NOTES: 7. SPI Interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period, and must be scaled proportionally for lower sample rates. 8. The SPI may operate asynchronously with respect to the ADC sample clock. 9. The Tri-Level Inputs internal switching thresholds are approximately .43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending on desired function. 10. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most applications. Contact factory for more info if needed. Read or Write Read or Write Read or Write Read or Write Read or Write tS tH tDS tDH
t CLK
CONDITION
SYMBOL L tOVR
MIN
TYP 7.5 1
MAX
UNITS cycles cycles
64 264 25 -4 -12 -4 -12 50 75
ns ns % ns ns ns ns
tCLK
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FN6807.2 March 4, 2009
KAD5512P Pinout/Package Information
Pin Descriptions - 72QFN
PIN NUMBER 1, 6, 12, 19, 24, 71 2-5, 13, 14, 17, 18, 28-31 7, 8, 11, 72 9, 10 15 16 20, 21 22 23 25 26, 45, 55, 65 27, 36, 56 32, 33 34, 35 37, 38 39, 40 41, 42 43, 44 46 47, 48 49, 50 51, 52 53, 54 57, 58 59, 60 61, 62 63, 64 66 67 68 69 70 Exposed Paddle LVDS [LVCMOS] NAME AVDD DNC AVSS VINN, VINP VCM CLKDIV CLKP, CLKN OUTMODE NAPSLP RESETN OVSS OVDD D0N, D0P [NC, D0] D1N, D1P [NC, D1] D2N, D2P [NC, D2] D3N, D3P [NC, D3] D4N, D4P [NC, D4] D5N, D5P [NC, D5] RLVDS CLKOUTN, CLKOUTP [NC, CLKOUT] D6N, D6P [NC, D6] D7N, D7P [NC, D7] D8N, D8P [NC, D8] D9N, D9P [NC, D9] D10N, D10P [NC, D10] D11N, D11P [NC, D11] ORN, ORP [NC, OR] SDO CSB SCLK SDIO OUTFMT AVSS LVDS [LVCMOS] FUNCTION 1.8V Analog Supply Do Not Connect Analog Ground Analog Input Negative, Positive Common Mode Output Tri-Level Clock Divider Control Clock Input True, Complement Tri-Level Output Mode Control (LVDS, LVCMOS) Tri-Level Power Control (Nap, Sleep modes) Power On Reset (Active Low, see page 17) Output Ground 1.8V Output Supply LVDS Bit 0 (LSB) Output Complement, True [NC, LVCMOS Bit 0] LVDS Bit 1 Output Complement, True [NC, LVCMOS Bit 1] LVDS Bit 2 Output Complement, True [NC, LVCMOS Bit 2] LVDS Bit 3 Output Complement, True [NC, LVCMOS Bit 3] LVDS Bit 4 Output Complement, True [NC, LVCMOS Bit 4] LVDS Bit 5 Output Complement, True [NC, LVCMOS Bit 5] LVDS Bias Resistor (connect to OVSS with a 10k, 1% resistor) LVDS Clock Output Complement, True [NC, LVCMOS CLKOUT] LVDS Bit 6 Output Complement, True [NC, LVCMOS Bit 6] LVDS Bit 7 Output Complement, True [NC, LVCMOS Bit 7] LVDS Bit 8 Output Complement, True [NC, LVCMOS Bit 8] LVDS Bit 9 Output Complement, True [NC, LVCMOS Bit 9] LVDS Bit 10 Output Complement, True [NC, LVCMOS Bit 10] LVDS Bit 11(MSB) Output Complement, True [NC, LVCMOS Bit 11] LVDS Over Range Complement, True [NC, LVCMOS Over Range] SPI Serial Data Output (4.7k pull-up to OVDD is required) SPI Chip Select (active low) SPI Clock SPI Serial Data Input/Output Tri-Level Output Data Format Control (Two's Comp., Gray Code, Offset Binary) Analog Ground
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection).
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FN6807.2 March 4, 2009
KAD5512P
Pinout
KAD5512P (72 LD QFN) TOP VIEW
OUTFMT OVDD 56 OVSS OVSS 55 54 D8P 53 D8N 52 D7P 51 D7N 50 D6P 49 D6N 48 CLKOUTP 47 CLKOUTN 46 RLVDS 45 OVSS 44 D5P 43 D5N 42 D4P 41 D4N 40 D3P 39 D3N 38 D2P 37 D2N 19 AVDD 20 CLKP 21 CLKN 22 OUTMODE 23 NAPSLP 24 AVDD 25 RESETN 26 OVSS 27 OVDD 28 DNC 29 DNC 30 DNC 31 DNC 32 D0N 33 D0P 34 D1N 35 D1P 36 OVDD AVDD SCLK AVSS D10N D10P D11N D11P SDIO ORN ORP SDO CSB D9N 57
72 AVDD DNC DNC DNC DNC AVDD AVSS AVSS VINN VINP AVSS AVDD DNC DNC VCM CLKDIV DNC DNC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
71
70
69
68
67
66
65
64
63
62
61
60
59
58
FIGURE 3. PIN CONFIGURATION
10
D9P
FN6807.2 March 4, 2009
KAD5512P
Pin Descriptions - 48QFN
PIN NUMBER 1, 9, 13, 17, 47 2-4, 11, 21, 22 5, 8, 12, 48 6, 7 10 14, 15 16 18 19, 29, 42 20, 37 23, 24 25, 26 27, 28 30 31, 32 33, 34 35, 36 38, 39 40, 41 43 44 45 46 Exposed Paddle LVDS [LVCMOS] NAME AVDD DNC AVSS VINN, VINP VCM CLKP, CLKN NAPSLP RESETN OVSS OVDD D0N, D0P [NC, D0] D1N, D1P [NC, D1] D2N, D2P [NC, D2] RLVDS CLKOUTN, CLKOUTP [NC, CLKOUT] D3N, D3P [NC, D3] D4N, D4P [NC, D4] D5N, D5P [NC, D5] ORN, ORP [NC, OR] SDO CSB SCLK SDIO AVSS 1.8V Analog Supply Do Not Connect Analog Ground Analog Input Negative, Positive Common Mode Output Clock Input True, Complement Tri-Level Power Control (Nap, Sleep modes) Power On Reset (Active Low, see page 17) Output Ground 1.8V Output Supply LVDS Bit 0 (LSB) Output Complement, True [NC, LVCMOS Bit 0] LVDS Bit 1 Output Complement, True [NC, LVCMOS Bit 1] LVDS Bit 2 Output Complement, True [NC, LVCMOS Bit 2] LVDS Bias Resistor (connect to OVSS with a 10k, 1% resistor) LVDS Clock Output Complement, True [NC, LVCMOS CLKOUT] LVDS Bit 3 Output Complement, True [NC, LVCMOS Bit 3] LVDS Bit 4 Output Complement, True [NC, LVCMOS Bit 4] LVDS Bit 5 Output Complement, True [NC, LVCMOS Bit 5] LVDS Over Range Complement, True [NC, LVCMOS Over Range] SPI Serial Data Output (4.7k pull-up to OVDD is required) SPI Chip Select (active low) SPI Clock SPI Serial Data Input/Output Analog Ground LVDS [LVCMOS] FUNCTION
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection).
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FN6807.2 March 4, 2009
KAD5512P
Pinout
KAD5512P (48 LD QFN) TOP VIEW
OVDD 37 36 D4P 35 D4N 34 D3P 33 D3N 32 CLKOUTP 31 CLKOUTN 30 RLVDS 29 OVSS 28 D2P 27 D2N 26 D1P 25 D1N 13 AVDD 14 CLKP 15 CLKN 16 NAPSLP 17 AVDD 18 RESETN 19 OVSS 20 OVDD 21 DNC 22 DNC 23 D0N 24 D0P OVSS AVDD SCLK AVSS SDIO ORN ORP SDO CSB D5N 38 D5P 39
48 AVDD DNC DNC DNC AVSS VINN VINP AVSS AVDD VCM DNC AVSS 1 2 3 4 5 6 7 8 9 10 11 12
47
46
45
44
43
42
41
40
FIGURE 4. PIN CONFIGURATION
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FN6807.2 March 4, 2009
KAD5512P Typical Performance Curves
90 HD2 AND HD3 MAGNITUDE (dBc) SNR (dBFS) AND SFDR (dBc) 85 80 75 70 65 60 55 50 0 200M 400M 600M 800M 1G INPUT FREQUENCY (Hz) SNR @ 250MSPS SFDR @ 250MSPS SNR @ 125MSPS SFDR @ 125MSPS
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum Conversion Rate (per speed grade).
-50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 0 200M HD3 @ 125MSPS HD3 @ 250MSPS 400M 600M 800M 1G HD2 @ 125MSPS HD2 @ 250MSPS
INPUT FREQUENCY (Hz)
FIGURE 5. SNR AND SFDR vs fIN
FIGURE 6. HD2 AND HD3 vs fIN
100 90 HD2 & HD3 MAGNITUDE 80 SNR AND SFDR 70 60 50 40 30 20 10 0 -60 -50 SNR (dBc) -40 -30 -20 -10 0 SFDR (dBc) SNRFS (dBFS) SFDRFS (dBFS)
-20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -60 HD3 (dBFS) -50 -40 -30 -20 -10 0 HD3 (dBc) HD2 (dBFS) HD2 (dBc)
INPUT AMPLITUDE (dBFS)
INPUT AMPLITUDE (dBFS)
FIGURE 7. SNR AND SFDR vs AIN
FIGURE 8. HD2 AND HD3 vs AIN
90 85 80 75 70 65 60 40 70 100 130 SNR
HD2 AND HD3 MAGNITUDE (dBc)
95 SNR (dBFS) AND SFDR (dBc) SFDR
-60 -70 -80 -90 -100 -110 -120 40
HD3
HD2
160
190
220
250
70
100
130
160
190
220
250
SAMPLE RATE (MSPS)
SAMPLE RATE (MSPS)
FIGURE 9. SNR AND SFDR vs fSAMPLE
FIGURE 10. HD2 AND HD3 vs fSAMPLE
13
FN6807.2 March 4, 2009
KAD5512P Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum Conversion Rate (per speed grade). (Continued)
1.5 SDR 250 TOTAL POWER (mW) 200 150 DDR 100 50 0 1.0 DNL (LSBs) 220 250 0.5 0 -0.5 -1.0 -1.5
300
40
70
100
130
160
190
0
512
1024
1536
2048 CODE
2560
3072
3584
4096
SAMPLE RATE (MSPS)
FIGURE 11. POWER vs fSAMPLE IN 3mA LVDS MODE
FIGURE 12. DIFFERENTIAL NONLINEARITY
1.5 1.0 INL (LSBs) 0.5 0 -0.5 -1.0 -1.5 0 512 1024 1536 2048 CODE 2560 3072 3584 4096 SNR (dBFS) & SFDR (dBc)
90 85 SFDR 80 75 70 65 60 55 50 300 400 500 600 700 800 SNR
INPUT COMMON MODE (mV)
FIGURE 13. INTEGRAL NONLINEARITY
FIGURE 14. SNR AND SFDR vs VCM
270000 240000
0 -20 AIN = -1.0dBFS SNR = 66.0dBFS SFDR = 82.5dBc SINAD = 65.9dBFS
210000 NUMBER OF HITS 180000 150000 120000 90000 60000 -100 30000 0 2050 2051 2052 2053 2054 CODE 2055 2056 2057 2058 -120 0 20 40 60 AMPLITUDE (dBFS) -40 -60 -80
80
100
120
FREQUENCY (MHz)
FIGURE 15. NOISE HISTOGRAM
FIGURE 16. SINGLE-TONE SPECTRUM @ 10MHz
14
FN6807.2 March 4, 2009
KAD5512P Typical Performance Curves
0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 0 AIN = -1.0dBFS SNR = 66.0dBFS SFDR = 86.5dBc SINAD = 65.9dBFS
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum Conversion Rate (per speed grade). (Continued)
0 -20 AMPLITUDE (dBFS) -40 -60 -80 AIN = -1.0dBFS SNR = 65.7dBFS SFDR = 79.2dBc SINAD = 65.4dBFS
-100 -120 20 40 60 80 100 120 FREQUENCY (MHz)
0
20
40
60
80
100
120
FREQUENCY (MHz)
FIGURE 17. SINGLE-TONE SPECTRUM @ 105MHz
FIGURE 18. SINGLE-TONE SPECTRUM @ 190MHz
0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 AIN = -1.0dBFS SNR = 64.4dBFS SFDR = 68.8dBc SINAD = 62.6dBFS
0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 0 AIN = -1.0dBFS SNR = 61.6dBFS SFDR = 49.8dBc SINAD = 49.8dBFS
0
20
40
60
80
100
120
20
40
60
80
100
120
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 19. SINGLE-TONE SPECTRUM @ 495MHz
FIGURE 20. SINGLE-TONE SPECTRUM @ 995MHz
0 IMD = -85.7dBFS -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -40 -60 -80 -100 -120
0 IMD = -97.1dBFS -20 -40 -60 -80 -100 -120 0
0
20
40
60
80
100
120
20
40
60
80
100
120
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 21. TWO-TONE SPECTRUM @ 70MHz
FIGURE 22. TWO-TONE SPECTRUM @ 170MHz
15
FN6807.2 March 4, 2009
KAD5512P Theory of Operation
Functional Description
The KAD5512P is based upon a 12-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (Figure 23). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge-domain techniques are used to successively compare the input to a series of reference charges. Decisions made during the successive approximation operations determine the digital code for each input value. The converter pipeline requires six samples to produce a result. Digital error correction is also applied, resulting in a total latency of seven and one half clock cycles. This is evident to the user as a time lag between the start of a conversion and the data being available on the digital outputs. A user-initiated reset can subsequently be invoked in the event that the previously mentioned conditions cannot be met at power-up. The SDO pin requires an external 4.7k pull-up to OVDD. If the SDO pin is pulled low externally during power-up, calibration will not be executed properly. After the power supply has stabilized, the internal POR releases RESETN and an internal pull-up pulls it high, which starts the calibration sequence. If a subsequent user-initiated reset is required, the RESETN pin should be connected to an open-drain driver with a drive strength of less than 0.5mA. The calibration sequence is initiated on the rising edge of RESETN, as shown in Figure 24. The over-range output (OR) is set high once RESETN is pulled low, and remains in that state until calibration is complete. The OR output returns to normal operation at that time, so it is important that the analog input be within the converter's full-scale range to observe the transition. If the input is in an over-range condition, the OR pin will stay high, and it will not be possible to detect the end of the calibration cycle. While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is set low. Normal operation of the output clock resumes at the next input clock edge (CLKP/CLKN) after RESETN is deasserted. At 250MSPS the nominal calibration time is 200ms, while the maximum calibration time is 550ms.
Power-On Calibration
The ADC performs a self-calibration at start-up. An internal power-on-reset (POR) circuit detects the supply voltage ramps and initiates the calibration when the analog and digital supply voltages are above a threshold. The following conditions must be adhered to for the power-on calibration to execute successfully: * A frequency-stable conversion clock must be applied to the CLKP/CLKN pins * DNC pins (especially 3, 4 and 18) must not be pulled up or down * SDO (pin 66) must be high * RESETN (pin 25) must begin low * SPI communications must not be attempted
CLOCK GENERATION
INP SHA INN
2.5-BIT FLASH
6-STAGE 1.5-BIT/STAGE
3-STAGE 1-BIT/STAGE
3-BIT FLASH
1.25V
+ -
DIGITAL ERROR CORRECTION
LVDS/LVCMOS OUTPUTS
FIGURE 23. ADC CORE BLOCK DIAGRAM
16
FN6807.2 March 4, 2009
KAD5512P
CLKN CLKP
4 SNR CHANGE (dBFS)
CALIBRATION TIME
3 2 1 0 -1 -2 -3 -4 -40 -15 10 35 60 85
RESETN CALIBRATION BEGINS ORP CALIBRATION COMPLETE CLKOUTP
FIGURE 24. CALIBRATION TIMING
TEMPERATURE (C) FIGURE 25. SNR PERFORMANCE vs TEMPERATURE AFTER +25C CALIBRATION
User-Initiated Reset
Recalibration of the ADC can be initiated at any time by driving the RESETN pin low for a minimum of one clock cycle. An open-drain driver with a drive strength of less than 0.5mA is recommended, RESETN has an internal high impedance pull-up to OVDD. As is the case during power-on reset, the SDO, RESETN and DNC pins must be in the proper state for the calibration to successfully execute. The performance of the KAD5512P changes with variations in temperature, supply voltage or sample rate. The extent of these changes may necessitate recalibration, depending on system performance requirements. Best performance will be achieved by recalibrating the ADC under the environmental conditions at which it will operate. A supply voltage variation of less than 100mV will generally result in an SNR change of less than 0.5dBFS and SFDR change of less than 3dBc. In situations where the sample rate is not constant, best results will be obtained if the device is calibrated at the highest sample rate. Reducing the sample rate by less than 75MSPS will typically result in an SNR change of less than 0.5dBFS and an SFDR change of less than 3dBc. Figures 25 and 26 show the effect of temperature on SNR and SFDR performance without recalibration. In each plot, the ADC is calibrated at +25C and temperature is varied over the operating range without recalibrating. The average change in SNR/SFDR is shown, relative to the +25C value.
15 SFDR CHANGE (dBc) 10 5 0 -5 -10 -15 -40
-15
10
35
60
85
TEMPERATURE (C) FIGURE 26. SFDR PERFORMANCE vs TEMPERATURE AFTER +25C CALIBRATION
Analog Input
The ADC core contains a fully differential input (VINP/VINN) to the sample and hold amplifier (SHA). The ideal full-scale input voltage is 1.45V, centered at the VCM voltage of 0.535V as shown in Figure 27. Best performance is obtained when the analog inputs are driven differentially. The common-mode output voltage, VCM, should be used to properly bias the inputs as shown in Figures 28 through 30. An RF transformer will give the best noise and distortion performance for wideband and/or high intermediate frequency (IF) inputs. Two different transformer input schemes are shown in Figures 28 and 29.
17
FN6807.2 March 4, 2009
KAD5512P
348O 69.8O 25O
1.8 1.4 1.0 0.6 0.2 0.725V INP VCM 0.535V
0.22F
INN
100O
CM
217O
KAD5512P VCM
100O 69.8O 348O
49.9O
25O 0.1F
FIGURE 27. ANALOG INPUT RANGE
FIGURE 30. DIFFERENTIAL AMPLIFIER INPUT
This dual transformer scheme is used to improve commonHmode rejection, which keeps the common-mode level of the input matched to VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differential input resistance of the KAD5512P is 1000.
ADT1-1WT ADT1-1WT
A differential amplifier, as shown in Figure 30, can be used in applications that require DC-coupling. In this configuration, the amplifier will typically dominate the achievable SNR and distortion performance.
Clock Input
The clock input circuit is a differential pair (see Figure 43). Driving these inputs with a high level (up to 1.8VPP on each input) sine or square wave will provide the lowest jitter performance. A transformer with 4:1 impedance ratio will provide increased drive levels. The recommended drive circuit is shown in Figure 31. A duty range of 40% to 60% is acceptable. The clock can be driven single-ended, but this will reduce the edge rate and may impact SNR performance. The clock inputs are internally self-biased to AVDD/2 to facilitate AC coupling.
200pF TC4-1W CLKP 1000pF
200O
1000pF
KAD5512P VCM
0.1F
FIGURE 28. TRANSFORMER INPUT FOR GENERAL PURPOSE APPLICATIONS
ADTL1-12 1000pF 1000pF
ADTL1-12 0.1F KAD5512P VCM
200pF
CLKN 200pF
FIGURE 29. TRANSMISSION-LINE TRANSFORMER INPUT FOR HIGH IF APPLICATIONS
FIGURE 31. RECOMMENDED CLOCK DRIVE
The SHA design uses a switched capacitor input stage (see Figure 42), which creates current spikes when the sampling capacitance is reconnected to the input voltage. This causes a disturbance at the input which must settle before the next sampling point. Lower source impedance will result in faster settling and improved performance. Therefore a 1:1 transformer and low shunt resistance are recommended for optimal performance.
A selectable 2X frequency divider is provided in series with the clock input. The divider can be used in the 2X mode with a sample clock equal to twice the desired sample rate. This allows the use of the Phase Slip feature, which enables synchronization of multiple ADCs.
TABLE 1. CLKDIV PIN SETTINGS CLKDIV PIN AVSS Float AVDD DIVIDE RATIO 2 1 4
The clock divider can also be controlled through the SPI port, which overrides the CLKDIV pin setting. Details on this are contained in "Serial Peripheral Interface" on page 22.
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FN6807.2 March 4, 2009
KAD5512P
A delay-locked loop (DLL) generates internal clock signals for various stages within the charge pipeline. If the frequency of the input clock changes, the DLL may take up to 52s to regain lock at 250MSPS. The lock time is inversely proportional to the sample rate. The 48-QFN package option contains six LVDS data outputs, and therefore can only support DDR mode. Additionally, the drive current for LVDS mode can be set to a nominal 3 mA or a power-saving 2 mA. The lower current setting can be used in designs where the receiver is in close physical proximity to the ADC. The applicability of this setting is dependent upon the PCB layout, therefore the user should experiment to determine if performance degradation is observed. The output mode and LVDS drive current are selected via the OUTMODE pin as shown in Table 2.
TABLE 2. OUTMODE PIN SETTINGS OUTMODE PIN
100 95 90 85 SNR (dB) 80 75 70 65 60 55 50 1 10 100 INPUT FREQUENCY (MHz) 1000 tj = 100ps tj = 10ps 10 BITS tj = 1ps 12 BITS
Jitter
In a sampled data system, clock jitter directly impacts the achievable SNR performance. The theoretical relationship between clock jitter (tJ) and SNR is shown in Equation 1 and is illustrated in Figure 32.
1 SNR = 20 log 10 ------------------- 2f t
IN J
(EQ. 1)
MODE LVCMOS LVDS, 3mA LVDS, 2mA
AVSS
tj = 0.1ps 14 BITS
Float AVDD
The output mode can also be controlled through the SPI port, which overrides the OUTMODE pin setting. Details on this are contained in "Serial Peripheral Interface" on page 22. An external resistor creates the bias for the LVDS drivers. A 10k, 1% resistor must be connected from the RLVDS pin to OVSS.
FIGURE 32. SNR vs CLOCK JITTER
This relationship shows the SNR that would be achieved if clock jitter were the only non-ideal factor. In reality, achievable SNR is limited by internal factors such as linearity, aperture jitter and thermal noise. Internal aperture jitter is the uncertainty in the sampling instant shown in Figure 1. The internal aperture jitter combines with the input clock jitter in a root-sum-square fashion, since they are not statistically correlated, and this determines the total jitter in the system. The total jitter, combined with other noise sources, then determines the achievable SNR.
Over Range Indicator
The over range (OR) bit is asserted when the output code reaches positive full-scale (e.g. 0xFFF in offset binary mode). The output code does not wrap around during an over-range condition. The OR bit is updated at the sample rate.
Power Dissipation
The power dissipated by the KAD5512P is primarily dependent on the sample rate and the output modes: LVDS vs. CMOS and DDR vs. SDR. There is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate. The output supply dissipation is approximately constant in LVDS mode, but linearly related to the clock frequency in CMOS mode. Figures 36 and 37 illustrate these relationships.
Voltage Reference
A temperature compensated voltage reference provides the reference charges used in the successive approximation operations. The full-scale range of each A/D is proportional to the reference voltage. The voltage reference is internally bypassed and is not accessible to the user.
Nap/Sleep
Portions of the device may be shut down to save power during times when operation of the ADC is not required. Two power saving modes are available: nap, and sleep. Nap mode is only available through SPI control, while Sleep mode can be selected with the pin or through SPI. Nap mode reduces power dissipation by approximately 70% (depending on operating state) and recovers to normal operation in approximately 1s. Sleep mode reduces power dissipation to less than 20mW but requires 1ms to recover. The clock should remain running and at a fixed frequency during Nap or Sleep. Recovery time from Nap mode will
FN6807.2 March 4, 2009
Digital Outputs
Output data is available as a parallel bus in LVDS-compatible or CMOS modes. Additionally, the data can be presented in either double data rate (DDR) or single data rate (SDR) formats. The even numbered output bits are active in DDR mode. When CLKOUT is low the MSB and all odd bits are output, while on the high phase the LSB and all even bits are presented. Figures 1 and 2 show the timing relationships for LVDS/CMOS and DDR/SDR modes.
19
KAD5512P
increase if the clock is stopped, since the internal DLL can take up to 52s to regain lock at 250MSPS. By default after the device is powered on, the operational state is controlled by the NAPSLP pin as shown in Table 3.
TABLE 3. NAPSLP PIN SETTINGS NAPSLP PIN AVSS Float AVDD MODE Normal Sleep Nap
Converting back to offset binary from Gray code must be done recursively, using the result of each bit for the next lower bit as shown in Figure 34.
GRAY CODE 11 10 9
****
1
0
****
The power-down mode can also be controlled through the SPI port, which overrides the NAPSLP pin setting. Details on this are contained in "Serial Peripheral Interface" on page 22. This is an indexed function when controlled from the SPI, but a global function when driven from the pin.
****
Data Format
Output data can be presented in three formats: two's complement, Gray code and offset binary. The data format is selected via the OUTFMT pin as shown in Table 4.
TABLE 4. OUTFMT PIN SETTINGS OUTFMT PIN AVSS Float AVDD MODE Offset Binary Two's Complement Gray Code
BINARY
11
10
9
****
1
0
FIGURE 34. GRAY CODE TO BINARY CONVERSION
Mapping of the input voltage to the various data formats is shown in Table 5.
TABLE 5. INPUT VOLTAGE TO OUTPUT CODE MAPPING INPUT TWO'S VOLTAGE OFFSET BINARY COMPLEMENT GRAY CODE
The data format can also be controlled through the SPI port, which overrides the OUTFMT pin setting. Details on this are contained in "Serial Peripheral Interface" on page 22. Offset binary coding maps the most negative input voltage to code 0x000 (all zeros) and the most positive input to 0xFFF (all ones). Two's complement coding simply complements the MSB of the offset binary representation. When calculating Gray code the MSB is unchanged. The remaining bits are computed as the XOR of the current bit position and the next most significant bit. Figure 33 shows this operation.
BINARY 11 10 9
-Full Scale 000 00 000 00 00 100 00 000 00 00 000 00 000 00 00 -Full Scale 000 00 000 00 01 100 00 000 00 01 000 00 000 00 01 + 1LSB Mid-Scale 100 00 000 00 00 000 00 000 00 00 110 00 000 00 00 +Full Scale - 1LSB +Full Scale 111 11 111 11 10 111 11 111 11 11 011 11 111 11 10 100 00 000 00 01 011 11 111 111 1 100 00 000 00 00
****
1
0
****
GRAY CODE
11
10
9
****
1
0
FIGURE 33. BINARY TO GRAY CODE CONVERSION
20
FN6807.2 March 4, 2009
KAD5512P
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A1
A0
D7
D6
D5
D4
D3
D2
D1D
0
FIGURE 35. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO
A0
A1
A2
A11
A12
W0
W1
R/W
D0
D1
D2
D3
D4
D5
D6
D7
FIGURE 36. LSB-FIRST ADDRESSING
tS tDS CSB tDH tHI
tCLK
tH
tLO
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
FIGURE 37. INSTRUCTION/ADDRESS PHASE
CSB STALLING CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 38. 2-BYTE TRANSFER
CSB
LAST LEGAL CSB STALLING
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 39. N-BYTE TRANSFER
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FN6807.2 March 4, 2009
KAD5512P Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate configuration of the device and to optimize performance. The SPI bus consists of chip select (CSB), serial clock (SCLK) serial data output (SDO), and serial data input/output (SDIO). The maximum SCLK rate is equal to the ADC sample rate (fSAMPLE) divided by 16 for write operations and fSAMPLE divided by 66 for reads. At fSAMPLE = 250MHz, maximum SCLK is 15.63MHz for writing and 3.79MHz for read operations. There is no minimum SCLK rate. The following sections describe various registers that are used to configure the SPI or adjust performance or functional parameters. Many registers in the available address space (0x00 to 0xFF) are not defined in this document. Additionally, within a defined register there may be certain bits or bit combinations that are reserved. Undefined registers and undefined values within defined registers are reserved and should not be selected. Setting any reserved register or value may produce indeterminate results. or written (see Table 6). The lower 13 bits contain the first address for the data transfer. This relationship is illustrated in Figure 37, and timing values are given in "Switching Specifications" on page 7. After the instruction/address bytes have been read, the appropriate number of data bytes are written to or read from the ADC (based on the R/W bit status). The data transfer will continue as long as CSB remains low and SCLK is active. Stalling of the CSB pin is allowed at any byte boundary (instruction/address or data) if the number of bytes being transferred is three or less. For transfers of four bytes or more, CSB is allowed stall in the middle of the instruction/address bytes or before the first data byte. If CSB transitions to a high state after that point the state machine will reset and terminate the data transfer.
TABLE 6. BYTE TRANSFER SELECTION [W1:W0] 00 01 BYTES TRANSFERRED 1 2 3 4 or more
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the data transfer. By default, all data is presented on the serial data input/output (SDIO) pin in three-wire mode. The state of the SDIO pin is set automatically in the communication protocol (described below). A dedicated serial data output pin (SDO) can be activated by setting 0x00[7] high to allow operation in four-wire mode. The SPI port operates in a half duplex master/slave configuration, with the KAD5512P functioning as a slave. Multiple slave devices can interface to a single master in four-wire mode only, since the SDIO output of an unaddressed device is asserted in three-wire mode. The chip-select bar (CSB) pin determines when a slave device is being addressed. Multiple slave devices can be written to concurrently, but only one slave device can be read from at a given time (again, only in four-wire mode). If multiple slave devices are selected for reading at the same time, the results will be indeterminate. The communication protocol begins with an instruction/address phase. The first rising SCLK edge following a high to low transition on CSB determines the beginning of the two-byte instruction/address command; SCLK must be static low before the CSB transition. Data can be presented in MSB-first order or LSB-first order. The default is MSB-first, but this can be changed by setting 0x00[6] high. Figures 35 and 36 show the appropriate bit ordering for the MSB-first and LSB-first modes, respectively. In MSB-first mode the address is incremented for multi-byte transfers, while in LSB-first mode it's decremented. In the default mode the MSB is R/W, which determines if the data is to be read (active high) or written. The next two bits, W1 and W0, determine the number of data bytes to be read
10 11
Figures 38 and 39 illustrate the timing relationships for 2-byte and N-byte transfers, respectively. The operation for a 3-byte transfer can be inferred from these diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG Bit ordering and SPI reset are controlled by this register. Bit order can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB first) to accommodate various microcontrollers. Bit 7 SDO Active Bit 6 LSB First Setting this bit high configures the SPI to interpret serial data as arriving in LSB to MSB order. Bit 5 Soft Reset Setting this bit high resets all SPI registers to default values. Bit 4 Reserved This bit should always be set high. Bits 3:0 These bits should always mirror bits 4:7 to avoid ambiguity in bit ordering. ADDRESS 0X02: BURST_END If a series of sequential registers are to be set, burst mode can improve throughput by eliminating redundant addressing. In 3-wire SPI mode the burst is ended by pulling the CSB pin high. If the device is operated in 2-wire mode the CSB pin is not available. In that case, setting the burst_end address determines the end of the transfer.
FN6807.2 March 4, 2009
22
KAD5512P
During a write operation, the user must be cautious to transmit the correct number of bytes based on the starting and ending addresses. Bits 7:0 Burst End Address This register value determines the ending address of the burst data. ADDRESS 0X22: GAIN_COARSE ADDRESS 0X23: GAIN_MEDIUM ADDRESS 0X24: GAIN_FINE Gain of the ADC core can be adjusted in coarse, medium and fine steps. Coarse gain is a 4-bit adjustment while medium and fine are 8-bit. Multiple Coarse Gain Bits can be set for a total adjustment range of +/- 4.2%. ( `0011' =~ -4.2% and `1100' =~ +4.2% ) It is recommended to use one of the coarse gain settings (-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the registers at 23h and 24h. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register.
TABLE 8. COARSE GAIN ADJUSTMENT 0x22[3:0] Bit3 Bit2 Bit1 Bit0 NOMINAL COARSE GAIN ADJUST (%) +2.8 +1.4 -2.8 -1.4
Device Information
ADDRESS 0X08: CHIP_ID ADDRESS 0X09: CHIP_VERSION The generic die identifier and a revision number, respectively, can be read from these two registers.
Indexed Device Configuration/Control
ADDRESS 0X10: DEVICE_INDEX_A A common SPI map, which can accommodate single-channel or multi-channel devices, is used for all Intersil ADC products. Certain configuration commands (identified as Indexed in the SPI map) can be executed on a per-converter basis. This register determines which converter is being addressed for an Indexed command. It is important to note that only a single converter can be addressed at a time. This register defaults to 00h, indicating that no ADC is addressed. Therefore Bit 0 must be set high in order to execute any Indexed commands. Error code `AD' is returned if any indexed register is read from without properly setting device_index_A. ADDRESS 0X20: OFFSET_COARSE ADDRESS 0X21: OFFSET_FINE The input offset of the ADC core can be adjusted in fine and coarse steps. Both adjustments are made via an 8-bit word as detailed in Table 7. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register.
TABLE 7. OFFSET ADJUSTMENTS PARAMETER Steps -Full Scale (0x00) Mid-Scale (0x80) +Full Scale (0xFF) Nominal Step Size 0x20[7:0] COARSE OFFSET 255 -133LSB (-47mV) 0.0LSB (0.0mV) +133LSB (+47mV) 1.04LSB (0.37mV) 0x21[7:0] FINE OFFSET 255 -5LSB (-1.75mV) 0.0LSB +5LSB (+1.75mV) 0.04LSB (0.014mV)
TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS PARAMETER Steps -Full Scale (0x00) Mid-Scale (0x80) +Full Scale (0xFF) Nominal Step Size 0x23[7:0] MEDIUM GAIN 256 -2% 0.00% +2% 0.016% 0x24[7:0] FINE GAIN 256 -0.20% 0.00% +0.2% 0.0016%
ADDRESS 0X25: MODES Two distinct reduced power modes can be selected. By default, the tri-level NAPSLP pin can select normal operation or sleep modes (refer to "Nap/Sleep" on page 19). This functionality can be overridden and controlled through the SPI. This is an indexed function when controlled from the SPI, but a global function when driven from the pin. This register is not changed by a Soft Reset.
TABLE 10. POWER-DOWN CONTROL VALUE 000 001 010 100 0x25[2:0] POWER DOWN MODE Pin Control Normal Operation Nap Mode Sleep Mode
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FN6807.2 March 4, 2009
KAD5512P
Nap mode must be entered by executing the following sequence:
SEQUENCE 1 2 3 4 REGISTER 0x10 0x25 0x10 0x25 VALUE 0x01 0x02 0x02 0x02
controlled through the SPI, as shown in Table 11. This register is not changed by a Soft Reset.
TABLE 11. CLOCK DIVIDER SELECTION VALUE 000 001 010 100 0x72[2:0] CLOCK DIVIDER Pin Control Divide by 1 Divide by 2 Divide by 4
Return to Normal operation as follows:
SEQUENCE 1 2 3 4 REGISTER 0x10 0x25 0x10 0x25 VALUE 0x01 0x01 0x02 0x01
ADDRESS 0X73: OUTPUT_MODE_A The output_mode_A register controls the physical output format of the data, as well as the logical coding. The KAD5512P can present output data in two physical formats: LVDS or LVCMOS. Additionally, the drive strength in LVDS mode can be set high (3mA) or low (2mA). By default, the tri-level OUTMODE pin selects the mode and drive level (refer to "Digital Outputs" on page 19). This functionality can be overridden and controlled through the SPI, as shown in Table 12. Data can be coded in three possible formats: two's complement, Gray code or offset binary. By default, the tri-level OUTFMT pin selects the data format (refer to "Data Format" on page 20). This functionality can be overridden and controlled through the SPI, as shown in Table 13. This register is not changed by a Soft Reset.
TABLE 12. OUTPUT MODE CONTROL VALUE 000 001 0x93[7:5] Pin Control LVDS 2mA LVDS 3mA LVCMOS
Global Device Configuration/Control
ADDRESS 0X71: PHASE_SLIP When using the clock divider, it's not possible to determine the synchronization of the incoming and divided clock phases. This is particularly important when multiple ADCs are used in a time-interleaved system. The phase slip feature allows the rising edge of the divided clock to be advanced by one input clock cycle when in CLK/4 mode, as shown in Figure 40. Execution of a phase_slip command is accomplished by first writing a `0' to bit 0 at address 71h followed by writing a `1' to bit 0 at address 71h (32 sclk cycles ).
CLK = CLKP - CLKN CLK 1.00ns CLK/4 4.00ns CLK/4 SLIP ONCE
010 100
TABLE 13. OUTPUT FORMAT CONTROL VALUE 000 001 010 100 0x93[2:0] OUTPUT FORMAT Pin Control Two's Complement Gray Code Offset Binary
CLK/4 SLIP TWICE
FIGURE 40. PHASE SLIP: CLK/4 MODE, fCLOCK = 1000MHz
ADDRESS 0X72: CLOCK_DIVIDE The KAD5512P has a selectable clock divider that can be set to divide by four, two or one (no division). By default, the tri-level CLKDIV pin selects the divisor (refer to "Clock Input" on page 18). This functionality can be overridden and
ADDRESS 0X74: OUTPUT_MODE_B ADDRESS 0X75: CONFIG_STATUS Bit 6 DLL Range This bit sets the DLL operating range to fast (default) or slow.
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KAD5512P
Internal clock signals are generated by a delay-locked loop (DLL), which has a finite operating range. Table 14 shows the allowable sample rate ranges for the slow and fast settings.
TABLE 14. DLL RANGES DLL RANGE Slow Fast MIN 40 80 MAX 100 fS MAX UNIT MSPS MSPS
ADDRESS 0XC0: TEST_IO Bits 7:6 User Test Mode These bits set the test mode to static (0x00) or alternate (0x01) mode. Other values are reserved. The four LSBs in this register (Output Test Mode) determine the test pattern in combination with registers 0xC2 through 0xC5. Refer to Table 16.
TABLE 15. OUTPUT TEST MODES 0xC0[3:0] OUTPUT TEST MODE Off Midscale Positive Full-Scale Negative Full-Scale Checkerboard Reserved Reserved One/Zero User Pattern 0x8000 0xFFFF 0x0000 0xAAAA N/A N/A 0xFFFF user_patt1 N/A N/A N/A 0x5555 N/A N/A 0x0000 user_patt2
The output_mode_B and config_status registers are used in conjunction to enable DDR mode and select the frequency range of the DLL clock generator. The method of setting these options is different from the other registers.
READ OUTPUT_MODE_B 0x74 READ CONFIG_STATUS 0x75 DESIRED VALUE
VALUE 0000 0001 0010 0011 0100
WORD 1
WORD 2
WRITE TO 0x74
0101 0110 0111 1000
FIGURE 41. SETTING OUTPUT_MODE_B REGISTER
The procedure for setting output_mode_B is shown in Figure 41. Read the contents of output_mode_B and config_status and XOR them. Then XOR this result with the desired value for output_mode_B and write that XOR result to the register.
ADDRESS 0XC2: USER_PATT1_LSB ADDRESS 0XC3: USER_PATT1_MSB These registers define the lower and upper eight bits, respectively, of the first user-defined test word. ADDRESS 0XC4: USER_PATT2_LSB ADDRESS 0XC5: USER_PATT2_MSB These registers define the lower and upper eight bits, respectively, of the second user-defined test word.
Device Test
The KAD5512 can produce preset or user defined patterns on the digital outputs to facilitate in-situ testing. A static word can be placed on the output bus, or two different words can alternate. In the alternate mode, the values defined as Word 1 and Word 2 (as shown in Table 15) are set on the output bus on alternating clock phases. The test mode is enabled asynchronously to the sample clock, therefore several sample clock cycles may elapse before the data is present on the output bus.
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SPI Memory Map
TABLE 16. SPI MEMORY MAP Addr (Hex) 00 SPI Config 01 02 03-07 Info 08 09 10 11-1F Indexed Device Config/Control 20 21 22 23 24 25 Parameter Name port_config reserved burst_end reserved chip_id chip_version device_index_A reserved offset_coarse offset_fine gain_coarse gain_medium gain_fine modes Reserved Medium Gain Fine Gain Power-Down Mode [2:0] 000 = Pin Control 001 = Normal Operation 010 = Nap 100 = Sleep other codes = reserved Reserved Reserved Reserved Reserved Next Clock Edge Clock Divide [2:0] 000 = Pin Control 001 = divide by 1 010 = divide by 2 100 = divide by 4 other codes = reserved Output Format [2:0] 000 = Pin Control 001 = Twos Complement 010 = Gray Code 100 = Offset Binary other codes = reserved DDR Enable 00h G Bit 7 (MSB) SDO Active Bit 6 LSB First Bit 5 Soft Reset Reserved Burst end address [7:0] Reserved Chip ID # Chip Version # Reserved Reserved Coarse Offset Fine Offset Coarse Gain cal. value cal. value cal. value cal. value cal. value 00h NOT affected by Soft Reset I I I I I I ADC00 Read only Read only 00h G G I 00h G Bit 4 Bit 3 Bit 2 Mirror (bit5) Bit 1 Mirror (bit6) Bit 0 (LSB) Mirror (bit7) Def. Value (Hex) 00h Indexed/ Global G
26-5F 60-6F 70 71
reserved reserved reserved phase_slip
72 Global Device Config/Control
clock_divide
00h NOT affected by Soft Reset
G
73
output_mode_A
Output Mode [2:0] 000 = Pin Control 001 = LVDS 2mA 010 = LVDS 3mA 100 = LVCMOS other codes = reserved DLL Range 0 = fast 1 = slow XOR Result
00h NOT affected by Soft Reset
G
74
output_mode_B
00h NOT affected by Soft Reset Read Only
G
75 76-BF
config_status reserved
XOR Result Reserved
G
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KAD5512P
TABLE 16. SPI MEMORY MAP (Continued) Addr (Hex) C0 Parameter Name test_io Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Def. Value (Hex) 00h Indexed/ Global G
User Test Mode [1:0] 00 = Single 01 = Alternate 10 = Reserved 11 = Reserved
Output Test Mode [3:0] 0 = Off 1 = Midscale Short 2 = +FS Short 3 = -FS Short 4 = Checker Board 5 = reserved 6 = reserved Reserved 7 = One/Zero Word Toggle 8 = User Input 9-15 = reserved
Device Test
C1 C2 C3 C4 C5 C6-FF
Reserved user_patt1_lsb user_patt1_msb user_patt2_lsb user_patt2_msb reserved B7 B15 B7 B15 B6 B14 B6 B14 B5 B13 B5 B13
00h B3 B11 B3 B11 B2 B10 B2 B10 B1 B9 B1 B9 B0 B8 B0 B8 00h 00h 00h 00h
G G G G G
B4 B12 B4 B12 Reserved
Equivalent Circuits
AVDD
AVDD
TO CLOCKPHASE GENERATION AVDD 11kO
18kO
CLKP
AVDD INP
F1 F2
CSAMP 1.6pF
TO CHARGE PIPELINE 3 F
1000O
AVDD INN
F1
CSAMP 1.6pF
F2
TO CHARGE PIPELINE F3
AVDD 11kO
18kO
CLKN
FIGURE 42. ANALOG INPUTS
AVDD AVDD AVDD
FIGURE 43. CLOCK INPUTS
75kO
AVDD
(20k PULL-UP ON RESETN ONLY)
TO SENSE LOGIC
OVDD OVDD
75kO 280O
OVDD 20k 280
TO LOGIC
INPUT
INPUT
75kO
75kO
FIGURE 44. TRI-LEVEL DIGITAL INPUTS
FIGURE 45. DIGITAL INPUTS
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KAD5512P Equivalent Circuits
OVDD 2mA OR 3mA OVDD DATA DATA D[11:0]P OVDD
(Continued)
OVDD
D[11:0]N
OVDD
DATA
DATA
DATA
D[11:0]
2mA OR 3mA
FIGURE 46. LVDS OUTPUTS
AVDD
FIGURE 47. CMOS OUTPUTS
VCM 0.535V + -
FIGURE 48. VCM_OUT OUTPUT
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies require extra care in PC board layout. Many complex board designs benefit from isolating the analog and digital sections. Analog supply and ground planes should be laid out under signal and clock inputs. Locate the digital planes under outputs and logic pins. Grounds should be joined under the chip.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance. Tantalum is a good choice. For best performance, keep ceramic bypass capacitors very close to device pins. Longer traces will increase inductance, resulting in diminished dynamic performance and accuracy. Make sure that connections to ground are direct and low impedance. Avoid forming ground loops.
LVDS Outputs
Output traces and connections must be designed for 50 (100 differential) characteristic impedance. Keep traces direct and minimize bends where possible. Avoid crossing ground and power-plane breaks with signal traces.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the analog input and clock signals. Locate transformers and terminations as close to the chip as possible.
Exposed Paddle
The exposed paddle must be electrically connected to analog ground (AVSS) and should be connected to a large copper plane using numerous vias for optimal thermal performance.
LVCMOS Outputs
Output traces and connections must be designed for 50 characteristic impedance.
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will not be operated do not require connection to ensure optimal ADC performance. These inputs can be left
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KAD5512P
floating if they are not used. Tri-level inputs (NAPSLP, OUTMODE, OUTFMT, CLKDIV) accept a floating input as a valid state, and therefore should be biased according to the desired functionality. Power Supply Rejection Ratio (PSRR) is the ratio of the observed magnitude of a spur in the ADC FFT, caused by an AC signal superimposed on the power supply voltage. Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one half the clock frequency, including harmonics but excluding DC. Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one-half the sampling frequency, excluding harmonics and DC. SNR and SINAD are either given in units of dB when the power of the fundamental is used as the reference, or dBFS (dB to full scale) when the converter's full-scale input power is used as the reference. Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS signal amplitude to the RMS value of the largest spurious spectral component. The largest spurious spectral component may or may not be a harmonic.
Definitions
Analog Input Bandwidth is the analog input frequency at which the spectral output power at the fundamental frequency (as determined by FFT analysis) is reduced by 3dB from its full-scale low-frequency value. This is also referred to as Full Power Bandwidth. Aperture Delay or Sampling Delay is the time required after the rise of the clock input for the sampling switch to open, at which time the signal is held for conversion. Aperture Jitter is the RMS variation in aperture delay for a set of samples. Clock Duty Cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. Differential Non-Linearity (DNL) is the deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) is an alternate method of specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it is calculated as: ENOB = (SINAD - 1.76)/6.02 Gain Error is the ratio of the difference between the voltages that cause the lowest and highest code transitions to the full-scale voltage less 2 LSB. It is typically expressed in percent. Integral Non-Linearity (INL) is the maximum deviation of the ADC's transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Least Significant Bit (LSB) is the bit that has the smallest value or weight in a digital word. Its value in terms of input voltage is VFS/(2N-1) where N is the resolution in bits. Missing Codes are output codes that are skipped and will never appear at the ADC output. These codes cannot be reached with any input value. Most Significant Bit (MSB) is the bit that has the largest value or weight. Pipeline Delay is the number of clock cycles between the initiation of a conversion and the appearance at the output pins of the data.
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KAD5512P Revision History
DATE 7/30/08 12/5/08 REVISION Rev 1 CHANGE Initial Release of Production Datasheet
FN6807.0 Converted to intersil template. Assigned file number FN6807. Rev 0 - first release (as preliminary datasheet) with new file number. FN6807.1 P1; revised Key Specs P2; added Part Marking column to Order Info P4; moved Thermal Resistance to Thermal Info table and added Theta JA Note 3 per packaging P4-6; revisions throughout spec tables. Removed note from Elec Specs (Nap Mode must be invoked using SPI.) Added notes 9 and 10 to Switching Specs. P9; revised function for Pin 22 OUTMODE, Pin 23 NAPSLP and Pin 70 OUTFMT P11; revised function for Pin 16 NAPSLP P13-15; Performance curves revised throughout P17; User Initiated Reset - revised 2nd sentence of 1st paragraph P19; Nap/Sleep - revised 1st and 2nd sentences of 2nd paragraph P23; Address 0x24: Gain_Fine; added 2 sentences to end of 1st paragraph. Revised Table 8 P22; Serial Peripheral Interface- 1st paragraph; revised 2nd and 4th sentences. P24; removed Figure (PHASE SLIP: CLK/2 MODE, fCLOCK = 500MHz) Address 0x71: Phase_slip; added sentence to end of paragraph P27; revised Fig 45 P27; Table 16; revised Bits7:4, Addr C0 Throughout; formatted graphics to Intersil standards FN6807.2 Changed "odd" bits N in Figure 1A - DDR to "even" bits N, Replaced POD L48.7x7E due to changed dimension from "9.80 sq" to "6.80" sq. in land pattern
12/23/08
2/25/09
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 30
FN6807.2 March 4, 2009
KAD5512P
Package Outline Drawing
L48.7x7E
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 2/09
7.00 PIN 1 INDEX AREA 6 A B 36 37 4X 5.50 PIN 1 INDEX AREA 6 48 1 44X 0.50
7.00
Exp. DAP 5.60 Sq.
(4X)
0.15
25 24 48X 0.40
TOP VIEW
12 13 48X 0.25 4 0.10 M C A B
BOTTOM VIEW
0.90 Max
SEE DETAIL "X" C 0.10 C 0.08 C SEATING PLANE
SIDE VIEW
44X 0.50
6.80 Sq C 48X 0.25 5.60 Sq 0 . 00 MIN. 0 . 05 MAX. 48X 0.60
DETAIL "X"
0 . 2 REF
5
TYPICAL RECOMMENDED LAND PATTERN
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
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KAD5512P
Package Outline Drawing
L72.10x10D
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 11/08
10.00 PIN 1 INDEX AREA 6 54 A 4X 8.50 B 55 72 1
68X 0.50
PIN 1 INDEX AREA 6
10.00
Exp. DAP 6.00 Sq.
37 (4X) 0.15 36
TOP VIEW
18 72X 0.40
BOTTOM VIEW
19 72X 0.24
4
0.10 M C A B
0.90 Max
SEE DETAIL "X" C 0.10 C 0.08 C SEATING PLANE
SIDE VIEW
68X 0.50
9.80 Sq
72X 0.24
6.00 Sq
C
0 . 2 REF
5
72X 0.60
0 . 00 MIN. 0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
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FN6807.2 March 4, 2009

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